1. Field of the Invention
This invention relates to methods for forming position alignment marks, and in particular for position alignment mark formation which can be useful in the manufacture of sticked-layer structure SOI (silicon on insulating substrate) devices requiring their silicon layers and back surface electrodes to be laid over and stuck together as they are formed.
2. Description of the Prior Art
In particular,, sticked-layer structure SOI devices composed of single-crystal silicon having both of its surfaces stuck to electrodes have a decisive advantage in improving and raising to a great degree the circuit integration of their resultant semiconductor LSIs.
Among the drawings attached to this invention, FIGS. 1 and 2 and their associates are simplified cross-sectional views of an SOI device of the above-described type, which may make clear its conventionally-employed processing method step by step.
As shown in FIG. 1(a), an SiO.sub.2 film on a silicon (Si) substrate is selectively etched to form a field zone (insulating zone) over the surface of the substrate 11 and is then subjected to thermal oxidation to form thereover a primary insulating layer 12 of oxidized silicon (SiO.sub.2 (I)). The silicon substrate thus processed is then, as shown in FIG. 1(b), masked over with a resist 17 and provided with a contact hole 20 which is cut therethrough to link the silicon layer with a back surface electrode layer. This contact hole 20 is positioned in an (active) element zone with its position aligned with respect to the end edge of the field zone.
As shown in FIG. 1(c), the silicon substrate is then stuck to polysilicon (poly-Si) which, through its patterning, forms the back surface electrode 13 in the contact hole 20.
As shown in FIG. 2(a) (just a reverse of its position as shown in FIG. 1(c)), the silicon substrate now has its entire surface covered over with a secondary insulating layer (SiO.sub.2 film (II)) 14. In turn, this SiO.sub.2 film (II) 14 is coated with a secondary poly-silicon (poly-si) layer which is a poly-Si layer 25. After having this layer polished, the silicon base is further stuck to a wafer 22 which forms a bed. The Si substrate 11 is ground and polished from the direction of its top surface (direction shown in the drawing with arrows) and its processing is completed when the SiO.sub.2 film (I) 12 is exposed, leaving in its active zone the Si substrate 11 which is now an Si layer. As shown in FIG. 2(b), the Si substrate 11 thereafter has formed thereover a gate insulating film 21 and a poly-Si gate electrode (surface electrode) 16. In this processing, the poly-Si gate electrode has its position aligned with respect to the end edge of the field zone.
According to the conventional manufacturing process as just described in the above, the contact hole 20 as shown in FIG. 1(b) and the poly-Si gate electrode 16 as shown in FIG. 2(b) need to be aligned with each other across the field zone, inevitably necessitating their respective positions to be aligned separately and making their alignment difference vulnerable to increase accordingly. This, in turn, makes it necessary to keep twice as much as allowance for an alignment gap margin between the contact hole 20 and the poly-Si electrode 16 as shown in FIG. 2(b), a fact which hampers the desired high-level circuit integration of SOI devices in a method presented herein as a reference to the prior art in the field the present invention relates to.